1. Field of the Invention
The present invention relates to semiconductor device fabrication. More particularly, the present invention relates to methods of forming a fine pattern of semiconductor devices, and methods of forming self-aligned contact (SAC).
2. Description of the Related Art
As the design requirements for fabricating semiconductor devices decrease, the processes for fabricating semiconductor devices have become increasingly complicated. Particularly, as misalignment margins of the photolithographic process decrease and the etching depth increase, when fine patterns such as a contact pad is formed, it is more difficult to form a fine contact. The SAC formation process is an alternative to producing misalignment margins.
In the SAC formation process, two or more different insulating materials are prepared, and a contact hole is formed using etch selectivity between the insulating materials. As the misalignment margin of the exposure process increases with the SAC formation process, it is easier to form a fine contact. The SAC formation process normally uses silicon oxide and silicon nitride as the different two insulating materials. For example, the SAC pad formation process of the DRAM device uses an etch selectivity between the silicon oxide interlayer insulating layer, and the silicon nitride capping layer, which forms the gate line or the bit line and the sidewall spacer. Thus, the alignment margins can be better achieved using the SAC formation process, despite the fineness of the pattern.
However, with the trend toward a higher integration of semiconductor devices, the aspect ratio of the contact hole becomes significantly increased. With the increase in the aspect ratio, the etch selectivity between the insulating materials used in the SAC formation process is also increased. For example, to perform the SAC formation process stably in a DRAM device, the etch selectivity of the etched material layer (silicon oxide layer) relative to the mask layer (silicon nitride layer) should be above 20 during the dry etching process. However, since an etch selectivity of a silicon oxide layer relative to a silicon nitride layer is generally about 12, the process margin is insufficient.
Significant efforts have been introduced to provide a higher etch selectivity. For example, the wall of the chamber in which the dry etching process is heated, so as to increase a concentration of CFx radical inside the plasma introduced as etchants. Further, new carbon fluoride based gases having a high C/F ratio, such as C4F8, C5F8, C3F6, or the like, maybe used as etchant. Moreover, new methods for suppressing the generation of excess F radicals due to over-dissociation of etchant inside the plasma by developing a new plasma source having a low electron temperature have been introduced.
However, all the above efforts provide an insufficient etch selectivity of about 10, and a high etch selectivity of above 20 cannot be achieved by the above methods. This is because the dry etching of the silicon oxide layer generates a physical etch, such as sputtering, more actively than a chemical etch, due to the substance properties of the silicon oxide layer. Normally, the high bias power in the range of about 500 to 2000 W is applied in order to etch the silicon oxide layer. As a result, a significant amount of sputtering occurs in the mask layer as well as the silicon oxide layer, by the CxFy gas, argon (Ar) gas, and/or oxygen (O2) gas in which a high bias power is applied. As a result, the capping layer and a sidewall spacer as etch masks are damaged, so that it is difficult to achieve a high etch selectivity above the required value of 20.
Besides, the photoresist layer may be deformed due to the strong sputtering effect. Since the thickness of the photoresist layer is decreased with the decrease in design requirements for fabricating semiconductor devices, the deformation of the photoresist layer due to the strong sputtering effect becomes more of a problem in semiconductor device fabrication. If the photoresist layer is deformed significantly, wiggling, striation, or the like may occur.
In order to solve the problem of photoresist deformation, a method of forming a polysilicon layer as an etch mask pattern has been introduced. However, that method is costly since the polysilicon layer is removed using a CMP or the like. Other problems also include high thermal budget and complicated formation processes. Further, the above method has limits in solving the problem of generating strong sputtering effects because it requires a high bias power to form the silicon oxide layer as the interlayer insulating layer, and it has a low etch selectivity relative to a hard mask layer due to its strong sputtering effect.